1. Field of the Invention
This invention relates to computer architecture. In particular, the invention relates to multi-thread computers.
2. Description of Related Art
Demand in high speed data transmission has given rise to many large bandwidth network protocols and standards. For example, the Synchronous Optical Network (SONET) has a number of standards used in Wide Area Network (WAN) with speeds ranging from a few megabits per second (Mbps) to several gigabits per second (Gbps). Popular standards include T1 (1.5 Mbps), T3 (45 Mbps), OC-3c (155 Mbps), OC-12c (622 Mbps), OC-48c (2.5 Gbps), OC-192c (10 Gbps), OC-768c (40 Gbps), etc.
In network applications, the requirements for cell processing and packet processing functions at line rates for broadband communications switches and routers have become increasingly difficult. Multiple processors are used in an arrangement that supports coordinated access to shared data to achieve the required level of performance.
A high performance processor typically has a number of resources associated with program execution. Examples of these resources include memory interface units, functional units, and instruction fetch units. Conflicts arise when use of resources is requested by several entities for the same operation cycle.
To complete the tasks involved in processing cells or packets in real time for communication applications, a processor should be able to apply its resources preferentially to the most pressing tasks.